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Rambus Delivers PCIe 6.0 Controller for Next-Generation Data Centers
- Pushes performance to 64 GT/s for advanced AI/ML, storage and networking applications
- Implements full PCIe 6.0 feature set with optimized power, area and latency
- Offers state-of-the-art data security with integrated IDE engine
SAN JOSE, Calif. – Jan. 26, 2022 – Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express® (PCIe®) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.
“The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”
Key features of the Rambus PCIe 6.0 Controller include:
- Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
- Supports fixed-sized FLITs that enable high-bandwidth efficiency
- Implements low-latency Forward Error Correction (FEC) for link robustness
- Internal data path size automatically scales up or down (256, 512, 1024 bits) based on max. link speed and width for reduced gate count and optimal throughput
- Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
- Supports Endpoint, Root-Port, Dual-Mode and Switch port configurations
- Integrated IDE optimized for performance
Interface IP PCIe 6.0 Controller
The PCI Express® (PCIe®) 6.0 Controller is configurable and scalable controller IP designed for ASIC implementation. The controller supports the PCIe 6.0 specification, including 64 GT/s data rates, PAM4 signaling, FLIT mode, and L0p power state. The PCIe 6.0 architecture will be essential for SoC designers creating next-generation chips that require the movement of large amounts of data within systems, including applications like HPC, cloud computing, artificial intelligence/machine learning (AI/ML), enterprise storage, networking, and automotive.
How the PCIe 6.0 Controller Works
The PCIe 6.0 controller is backward compatible to the PCIe 5.0, 4.0 and 3.1/3.0 specifications. It supports version 6.x of the PHY Interface for PCI Express (PIPE) specification. The controller exposes a highly efficient transmit (Tx) and receive (Rx) interface with configurable bus widths. Designed to satisfy a multitude of customer and industry use cases, the IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters.
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