JEDEC publishes DDR5 SDRAM standard update with new features and timings definitions for 6400 MT/s and 5600 MT/s speeds

Published: 27th Oct 2021, 06:42 GMT   Comments

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JEDEC Publishes Update to DDR5 SDRAM Standard Used in High-Performance Computing Applications

ARLINGTON, Va., USA – OCTOBER 26, 2021 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5A DDR5 SDRAM standard. This update to the JEDEC DDR5 SDRAM standard includes features designed to enhance reliability and performance in a wide range of applications involving client systems and high-performance servers. JESD79-5A is now available for download from the JEDEC website.

Added features designed to meet industry demand for improved system reliability include bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension.

JESD79-5A expands the timing definition and transfer speed of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings to enable the industry to build an ecosystem up to 5600 MT/s. The nomenclature for core timing parameters and their respective definitions has been revamped to closely align with the upcoming JEDEC JESD400-5 DDR5 Serial Presence Detect (SPD) Contents V1.0 standard.

“The fact that this update to DDR5 is being published so soon after the initial launch of DDR5 in July 2020 underscores JEDEC’s ongoing commitment to continual improvement, and represents a collective effort on the part of all involved member companies to better serve the industry,” said Mian Quddus, JEDEC Chairman.

Industry Support

“AMD is proud of our ongoing collaboration with JEDEC, driving the high-performance computing industry forward with powerful improvements to DDR5 features. With the new JESD79-5A DDR5 standard, JEDEC offers the most advanced memory for high performance and reliability and continues our joint commitment to enabling the best possible experiences for end users.”

said Joe Macri, Chief Technology Officer, Compute and Graphics Business Unit, AMD.

“Intel is committed to advanced technology innovations that will greatly benefit the industry and our customers. DDR5 represents the next advancement in mainstream memory technology that will be featured in future client and server platforms. Working with our ecosystems partners and standards associations like JEDEC help end customers to accelerate adoption of new technologies and achieve breakthrough computing performance.”

said Carolyn Duran, VP – Data Platforms Group, GM – Memory and IO Technologies at Intel.

“Close collaboration is required to deliver the system-level reliability and scale-up performance that data-centric workloads demand from DDR5. Micron is proud to work with JEDEC and a broad ecosystem to advance memory standards that empower customers to turn their data into insights faster.”

said Frank Ross, lead architect at Micron.

“Samsung is proud to see that DDR5 memory will be able to reach new heights in operating efficiency and self-correcting capabilities, something that we and other industry leaders have been working intently to standardize over the past 14 months. With these enhancements, the industry is setting an extremely firm foundation for one of the most ambitious memory upgrades ever ― an advancement particularly important for large server systems,” he added.

said Young-Soo Sohn, vice president of the DRAM Memory Planning/Enabling Group at Samsung Electronics.

“As new reliability features have now become part of the DDR5 standard, SK hynix is pleased to be able to provide a more robust memory solution to our customers. Furthermore, being able to deliver higher device speeds will bring the overall system performance to the next levels. SK hynix has been providing DDR5 DIMM samples to the industry since 2019 for ecosystem readiness, and will continue to actively participate in future JEDEC activities for continued open innovation and ecosystem enabling,”

said Uksong Kang, Head of DRAM Product and Planning at SK hynix.

« end of the press release »

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