AMD discusses Second Generation 3D V-Cache
AMD has confirmed new details on their new 3D V-Cache technology used by Ryzen 7000X3D series.
It has been almost a week since the launch of the Ryzen 7000X3D series. AMD has been an open book to reviewers and provided all the necessary details that consumers might have wanted to know. However, there were still some details that might not be as important to end users, but still very interesting to the tech community nonetheless.
Over the weekend, AMD has provided further details on the 3D V-Cache technology as well as published the very first picture of the new I/O die, the third chiplet accompanying dual 8-core consumer CPUs codenamed Raphael. Some of these details were provided to Tom’s Hardware who asked the company directly, while the remaining details were confirmed during the 2023 International Solid-State Circuits Conference (ISSCC).
The 3D V-Cache on Ryzen 7000 series expands the Level 3 cache up to 96MB for one of the chiplets. The Cache itself is designed in 7nm process node, while it is placed on top of the 5nm Zen4 CCD. The second generation cache die is actually smaller than first gen, while retaining the same transistor count. This means that the transistor density has increased from 114.6M to 130.6 MTr/mm².
|Second-Gen 3D V-Cache Technology AMD Ryzen 9 7950X3D|
|Tom’s Hardware||2nd-Gen 7nm 3D V-Cache Die||First-Gen 7nm 3D V-Cache Die||5nm Zen 4 Core Complex Die (CCD)||7nm Zen 3 Core Complex Die (CCD)|
|Transistor Count||~4.7 Billion||4.7 Billion||6.57 Billion||4.15 Billion|
|MTr/mm^2 (Transistor Density)||~130.6 Million||~114.6 Million||~99 Million||~51.4 Million|
AMD has also confirmed that the new Cache has higher bandwidth reaching as high as 2.5 TB/s. That’s 25% or 0.5 TB/s improvement over the 5800X3D cache die design. Furthermore, due to changes in design, AMD had to alter the TSV (Through Silicon Vias) connections as well. AMD had to shrink the TSV area by 50%.
AMD is using the same Zen4 CCDs on Ryzen and EPYC series, but the I/O die has been modified for consumers and data center environments accordingly. A picture of the consumer I/O die has been shared with the slide deck as well.
This die shot has been added to the ISSCC presentation, and was quickly analyzed by hardware detective Locuza, who provided proper annotations. It shows how large the integrated GPU and confirms it is indeed limited to 128 cores. It is further confirmed that the I/O die only has two GMI (Global Memory Interconnect) ports, therefore no triple CCD configurations are possible with this chiplet.
Source: Tom’s Hardware, @Locuza, TechSpot