The Peripheral Component Interconnect Special Interest Group (PCI-SIG) consortium released new information on the upcoming PCIe 6.0 interface standard specifications. The consortium’s board of directors has representatives from manufacturers such as AMD, NVIDIA and Intel.
PCI Express 4.0 (PCIe 4.0)
We are yet to see the full adoption of the PCIe 4.0 standard. As of today, only AMD introduced both CPUs and GPUs compatible with the new interface. Their Radeon RX 5000 series are all PCIe 4.0 compatible, the same applies to X570 and B550 motherboards.
Intel is expected to launch first PCIe 4.0 compatible processors based Rocket Lake-S architecture early next year, while its Z490 motherboard series is already “hardware-ready” for the standard, just not for the 10th Gen Core series. Intel’s first PCIe 4.0 compatible server processors are Ice Lake-SP, expected later this year.
In May, NVIDIA introduced the A100 Tensor Core processor featuring PCIe 4.0 interface. The upcoming Ampere RTX series is also expected to support PCIe 4.0 standard at the release.
PCI Express 5.0 (PCIe 5.0)
AMD and Intel have not publicly confirmed when PCIe 5.0 compatible devices will be available. However, what we know from leaked roadmaps is that Intel should support PCIe 5.0 with Sapphire Rapids architecture.
The PCIe 5.0 standard will double the bandwidth of 4.0 while retaining backward compatibility up to 1.0 standard. The development and adoption of the PCIe 5.0 standard is progressing as we speak. PCI-SIG is still developing necessary compliance testing equipment.
PCI Express 6.0 (PCIe 6.0)
Similarly to PCIe 5.0, the 6.0 specifications feature doubled bandwidth over predecessor (64 GT/s). The backward compatibility is also to be kept up to 1.0 standard.
Increased bandwidth comes from PAM4 signaling adoption for the standard. This 2-bit encoding will increase the bandwidth by packing more bits into the stream. The PAM4 adoption means that the error correction is also necessary, that’s why PCIe 6.0 will also feature Forward Error Correction (FEC). Both technologies should improve reliability and bandwidth efficiency at the same time.
The 6.0 standard was designed for high-bandwidth applications, such as large scale computing where Artificial Intelligence and Machine Learning hardware is connected. The presentation slide also lists 800G Ethernet support with the new PCIe standard.
PCI-SIG has released a 0.5 draft and a 0.7 draft is expected later this year. The consortium expects to finalize the 1.0 specifications of the PCIe 6.0 standard in 2021.