NVIDIA GH100 Hopper: only one GPC with graphics enabled
An interesting part of the NVIDIA leak has just resurfaced.
Twitter user Locuza specializing in creating visual summaries of the existing knowledge on upcoming hardware products, has made a new GPU diagram featuring NVIDIA GH100 GPU, the upcoming data-center accelerator and company’s first 5 nm processor.
His diagram features two details that have been revealed in the past 2 weeks, details that we have missed. The origin of this leak is not official data, but the information that has leaked after hacking group published leaked confidential data from NVIDIA servers.
Although NVIDIA is more than likely to announce its Hopper GPUs tomorrow, some details might not immediately be confirmed. For instance, the fact that only one Graphics Processing Cluster (GPC) has a 3D engine, while 7 do not. This means that not all GPCs in Hopper GPU are identical, and NVIDIA is clearly saving space for a functionality that is simply not as important for a datacenter GPU as it would have been for a consumer product.
NVIDIA GH100 GPC configuration, Source: @xinoassassin1
Furthermore, it is said that GH100 GPU would feature 48 MB of L2 Cache. This is not an upgrade over Ampere GA100 GPU (48MB) though. However, it is three times as much as AMD’s Instinct MI250 “Aldebaran” GPU with 16MB of total L2 cache. Interestingly, NVIDIA’s RTX 40 series codenamed “Ada” are rumored to feature even more L2 cache, up to 96MB for AD102 GPU.
Thanks to the leak, NVIDIA GH100 is confirmed to feature 8 GPCs. Each cluster is to feature 9 TPCs and each TPC comes with two Streaming Multiprocessors. Now assuming that the architecture has not changed in regard to CUDA cores, this would give 144 SMs and 9216 CUDA cores (or 17152 if FP32 cores are doubled).
NVIDIA GH100 GPU Block Diagram, Source: @Locuza
It is worth noting that GH100 is a single die chip (monolithic), whereas the rumored GH202 is a MCM design, possibly featuring two GH100 dies. Naturally, the end-product such as H100 Tensor Core for SXM or PCIe accelerator would not have the full 144 SMs enabled. It is expected that around 15 to 20% of SMs will be disabled.
NVIDIA is to unveil Hopper architecture at GTC tomorrow during CEO Jensen Huang’s keynote at GTC 2022.
| RUMORED NVIDIA Data-Center GPUs Specifications | ||||
|---|---|---|---|---|
| VideoCardz.com | NVIDIA H100 | NVIDIA A100 | NVIDIA Tesla V100 | NVIDIA Tesla P100 |
| Picture |  |  |  |  |
| GPU | GH100 | GA100 | GV100 | GP100 |
| Transistors | 80B | 54.2B | 21.1B | 15.3B |
| Die Size | 814 mm² | 828 mm² | 815 mm² | 610 mm² |
| Architecture | Hopper | Ampere | Volta | Pascal |
| Fabrication Node | TSMC N4 | TSMC N7 | 12nm FFN | 16nm FinFET+ |
| GPU Clusters | 132 | 108 | 80 | 56 |
| CUDA Cores | 16896/14592* | 6912 | 5120 | 3584 |
| L2 Cache | 50MB | 40MB | 6MB | 4MB |
| Tensor Cores | 528/456* | 432 | 320 | – |
| Memory Bus | 5120-bit | 5120-bit | 4096-bit | 4096-bit |
| Memory Size | 80 GB HBM3/HBM2e* | 40/80GB HBM2e | 16/32 HBM2 | 16GB HBM2 |
| TDP | 700W/350W* | 250W/300W/400W | 250W/300W/450W | 250W/300W |
| Interface | SXM5/*PCIe Gen5 | SXM4/PCIe Gen4 | SXM2/PCIe Gen3 | SXM/PCIe Gen3 |
| Launch Year | 2022 | 2020 | 2017 | 2016 |
Source: @Locuza, @xinoassassin1
