More information on Intel’s next-generation mobile architecture.
Intel Tiger Lake features SuperFin
We have more details on Intel’s upcoming Tiger Lake architecture. The series will be announced on September 2nd during a special virtual event. In the meantime, we have gathered new information from our sources.
Intel has set a number of goals for its next mobile series, including: greater CPU and GPU performance, scalability for different workloads, increased memory and fabric efficiency, advances in security, and more.
All this combined is to expected deliver a significant upgrade to the 10nm mobile series.
SuperFin and SuperMIM
The most significant improvement, however, is hidden in a fabrication node itself. Intel is calling it the 10nm SuperFin architecture because it features a redesigned transistor (SuperFin) and capacitor design (Super MIM). According to people familiar with the matter, this intranode architecture will provide a performance uplift comparable to a full-node transition. A redefined FinFET will provide additional gate pitch (higher drive current), improved gate process (higher channel mobility), and enhanced expiation source/drain (lower resistance). Additionally, 10nm SuperFin architecture will benefit from the introduction of Super MIM capacitor, delivering 5x the increase in MIM (metal-insulator-metal) capacitance.
The company is developing a 10nm Enhanced SuperFin architecture, promising additional performance, interconnect innovations, and optimization for data centers.
Intel SuperFin transistor and Super MIM capacitor (left), Source: Raja Koduri
Willow Cove core architecture
Intel Tiger Lake will also benefit from core architecture upgrade to Willow Cove, which was built upon Sunny Cove design (Ice Lake). It features a redesigned middle-level cache of 1.25MB, as we already seen in the leaks. It also features Control-Flow Enforcement technology to increase security against return/jump oriented attacks.
More importantly, Intel confirmed that Tiger Lake will feature ‘dramatic frequency increase over prior generation’. The Willow Cove core will deliver higher frequency at lower voltages than Sunny Cove.
Intel Xe-LP Graphics
Tiger Lake’s integrated graphics were built upon next-generation Xe graphics architecture. The Tiger Lake SoC features up to 96 Execution Units, compared to last-gen’s maximum of 64. The GPU chip features 3.8MB of L3 cache.
Memory and bandwidth
It is said that Tiger Lake was designed for high bandwidth, which required further innovations in fabric and memory throughput within the silicon. The coherent fabric (ring) bandwidth was doubled compared to Ice Lake. The memory subsystem now supports up to 86GB/s of bandwidth with architectural support for LP4x-4267, DDR4-3200 and LP5-5400.
Display, GNA 2.0 and IO
The Xe-LP architecture display engine supports more displays connected to the SoC at higher resolutions and quality. It can handle videos up to 4K30 initially with plans for up to 4K90 support and images up to 42 Megapixels with initial 27 MP support.
Intel Tiger Lake also features Gaussian and Neural Accelerator 2.0 for various AI operations such as high dynamic range noise cancellation.
As promised, Intel Tiger Lake supports Thunderbolt 4 and USB4. Each port has a bandwidth of up to 40 Gb/s. The USB Type-C will support Displayport alternative mode, DP tunneling over Thunderbolt, and DP-in ports for discrete graphics card display output to mux over the C port. Tiger Lake is Intel’s first architecture to support PCIe 4.0.
