Intel APX, AVX10.1 and AV10.2
It is stated that the first Intel product with initial support for new instructions will be the next-gen Xeon codenamed Granite Rapids.
In the “Introducing Intel Advanced Performance Extensions (Intel APX)” article on the developer portal, Intel provides four documents in the footnotes. These documents vary in length, ranging from a concise seven pages to a more extensive 1,310 pages. It is a large data set that ultimately explains how Intel is planning to retain AVX512 instructions with necessary enhancements for its future products.
The company Advanced Performance Extensions (APX), which increases the general-purpose register count from 16 to 32. According to Intel’s explanation, code compiled with APX experiences 10% fewer loads and 20% fewer stores compared to the Intel 64 baseline. This means that APX code not only executes faster but also consumes less dynamic power, making it an interesting option for performance-conscious developers.
One of the key advantages of APX is that software recompiled with these extensions requires no significant changes to the code. This makes optimizations for the new extensions as simple as recompiling the software, ensuring a seamless upgrade process for developers and enabling them to take advantage of the benefits of APX with minimal effort.
With the introduction of Granite Rapids, the transition to the new instructions will not occur all at once. Instead, the older instructions will be retained through legacy support under AVX10.1 ISA.
Intel has set a goal for implementing advanced instructions for its Efficient cores as well. This is particularly important because the company plans to introduce its E-Core only Sierra Forest series next year. However, these instructions are expected to drop later, possibly when the Sierra’s successor, Clearwater Forest architecture is released.
The company has confirmed that the development of AVX10 ISA will optimally support both the Client and Server products. Intel’s hybrid architecture of P and E-cores already spans across from Core to Xeon. A new instruction set that can expand support for modern instructions would definitely simplify the development of software for these platforms.