Intel Rialto Bridge features 160 Xe-Cores, sampling starts in 2023
Today at ISC 2022 in Germany, Intel has unveiled its plans for a next-gen data center GPU accelerator.
Ponte Vecchio, which is set to launch by the end of this year, already has a successor codenamed Rialto Bridge. Today’s announcement is a confirmation of a rumor from March, where such a codename was first mentioned. This next-gen HPC accelerator, which is an evolution of Ponte Vecchio, will feature up to 160 Xe-Cores.
Intel claims that their new GPU will feature enhanced tiles with next process node, with increased density, performance, and efficiency. Intel did not confirm which node specifically does Rialto Bridge use, but one could guess it is Intel 4.
With 160 Xe-Cores, the core count has increased by 25% over Ponte Vecchio. Furthermore, Intel confirms Rialto will have increased I/O bandwidth and it most likely features HBM3 memory, which would be the second HPC GPU with this type of memory following NVIDIA Hopper.
Rialto Bridge is to feature OAM v2 form factor, which could support up to 800W. Interestingly, Intel promises that Rialto will be compatible with existing Ponte Vecchio subsystems.
Intel is targeting up to 30% increase for applications, but the company did not specify which applications would this performance target focus on. Such improvement is just 5% higher than Xe-Core count, so further improvements may be expected from a newer node and increased clock speed.
The company confirmed that Rialto Bridge will start sampling in mid-2023, but no date was provided. One might wonder if Intel will hit its targets this time, as Ponte Vecchio which was introduced more than 2 years ago, is still not available with Aurora 2 system.
| 2022-2023 HPC GPUs | ||||
|---|---|---|---|---|
| VideoCardz.com | NVIDIA H100 SXM | AMD Instinct MI250X OAM | Intel Ponte Vecchio OAM | Intel Rialto Bridge OAM |
| Picture |  |  |  |  |
| GPU | GH100 | Aldebaran (MCM) | Ponte Vecchio (MCM) | Rialto Bridge (MCM) |
| Transistors | 80B | 58.2B | 100B | TBC |
| Die Size | 814 mm² | 2x ~790 mm² | 2x 640 mm² | TBC |
| Architecture | Hopper | CDNA2 | Xe-HPC | Xe-HPC |
| Fabrication Node | TSMC N4 | TSMC N6 | Intel 7, TSMC N5/N7 | Intel 4 (?) |
| GPU Clusters | 132 (SMs) | 220 (CUs) | 128 Xe-Cores | 160 Xe-Cores |
| L2 Cache | 50MB | 32MB | 408 MB | TBC |
| Tensor/Matrix Cores | 528 | 2x 440 | 128 | 160 |
| Memory Bus | 5120-bit | 8192-bit | 8192-bit | 8192-bit (?) |
| Memory Size | 80 GB HBM3 | 128GB HBM2e | 128GB HBM2e | HBM3 |
| TDP | 700W | 560W | ~600W | ~800W |
| Interface/Form Factor | SXM5/PCIe Gen5 | OAM/PCIe Gen5 | OAM/PCIe Gen5 | OAM V2 |
| Launch Year | 2022 | 2021 | 2022 | 2023 |
