Intel Meteor Lake with L4 cache
The patent confirms the use of “Adamantine” cache for Meteor Lake.
Intel has already confirmed the use of Level 4 caches for its upcoming System on a Chip codenamed Meteor Lake. This was first reported by Phoronix in the recent Linux patches. Other than confirming the return of L4 cache on processors, similar to eDRAM that we had on the Intel Broadwell platform, the details on Meteor Lake implementations are missing.
As it turns out, Intel had already filed a patent that may explain the use of such cache. According to the patent from December 2020, the ‘next-generation SoC architecture’ aka Meteor Lake is to feature ‘on-package caches’. In other words, the Adamantine cache would be part of the base tile that could be accessed by any of the building blocks of next-gen SoC.
Meteor Lake, Source: Intel
Meteor Lake will fully embrace the hybrid architecture combining five different tiles: CPU, SoC, GPU, I/O and base tile. The Adamantine cache would offer much faster access time than any typical cache like L3, which is typically part of the CPU tile.
As explained by Intel, the main purpose of L4 cache is to improve boot optimization and increase security around the host CPU. Furthermore, the L4 cache would preserve the cache at reset, leading to improved loading times that would otherwise have to go through all boot/reset cycles.
Next generation client SoC architectures may introduce large on-package caches, which will allow novel usages. Access time for the L4 (e.g., “Adamantine” or “ADM”) cache may be much less than the DRAM access time, which is used to improve host CPU and security controller communications. Embodiments help to protect innovations in boot optimization. Value is added for high end silicon with higher pre-initialized memory at reset, potentially leading to increased revenue. Having memory available at reset also helps to nullify legacy BIOS assumptions and make a faster and efficient BIOS solution with a reduced firmware stage (e.g., pre-CPU reset stage, IBBL stage and IBB stage) for modern device use cases like Automotive IVI (in-vehicle infotainment, e.g., turn on rear view camera within 2 sec), household and industrial robots, etc. Accordingly, new market segments may be available.
The patent is attached to a block diagram clearly confirming we are looking at a Meteor Lake with 2 RWC (Redwood Cove) and 8 CMT (Crestmont) cores. Interestingly, the SOC tile is also shown to feature two CMT cores, which was already mentioned by early leaks. This particular design would also have Gen 12.7 Xe graphics with 64 EUs.
Meteor Lake, Source: Intel
The Adamantine cache was also mentioned by Moore’s Law is Dead in his latest video, who claims that the cache could expand into ‘gigabytes’, but it is currently tested with in sizes of 128MB to 512MB.
Officially, Intel Meteor Lake is now expected to launch in the second half of 2023. However, the company did not confirm which series of Meteor Lake would be introduced first.
Source: Intel Patent
