Alder Lake Series
Intel is developing three Alder Lake series, two being mobile-oriented. There have been a lot of leaks on the desktop parts, but mobile Alder Lake has so far managed to avoid significant exposures. What we do know is that Alder Lake will feature high performance (big) and high efficiency (small) cores in a special hybrid configuration. The number of cores will depend on the processor’s purpose.
SiSoftware Sandra 20 R14 30.92 now supports Intel’s Hybrid architecture. The developer has confirmed today that all three variants of Alder Lake are now supported by the software, which should provide more insight and accurate readings for the upcoming leaks.
SiSoftware Sandra 20 R14 30.92 Changelog:
- Intel Alderlake (ADL-S/P/M) support; optimised RocketLake (RKL-S/U) support
- AMD Ryzen (ZenX+) support; optimised Zen3 support
- big/LITTLE hybrid system workload optimisation
- Future AVX512-FP16 benchmarks
The desktop Alder Lake-S series will offer a maximum of 8 big and 8 small cores, but only the big cores will support hyperthreading. That said, the CPU will offer up to 16 total cores and 24 threads. The ADP-S series will offer GT1 graphics based on Xe architecture, possibly limited to 32 Execution Units. The S-Series are designed for desktop environments. Intel has already demoed the system during its CES 2021 presentation.
Meanwhile, the mobile series is to be divided into P and M sub-series. The Alder Lake-M series is considered a low-power Lakefield successor, although it has not yet been fully confirmed. Those CPUs will be limited to 2 big cores and up to 8 small cores. The series shall feature GT2 graphics likely with 96 Execution Units.
The Alder Lake-P series might feature up to 6 big cores and 8 small cores. The series might be offered alongside Tiger Lake-H (45W) at some point in the future. We have already seen leaks where Alder Lake-P was paired with yet unannounced Intel DG2 GPU, the upcoming high-performance discrete Xe-HPG graphics solution.
Alder Lake-M has recently been confirmed through Coreboot to support 10 PCH PCIe lanes. This confirms that the sub-architecture has fewer lanes than both the M and S series.
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
default 3
config MAX_ROOT_PORTS
int
default MAX_PCH_ROOT_PORTS
config MAX_PCIE_CLOCKS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
default 12
All three sub-architectures are likely to be launch under the 12th Gen Core series. It is unclear if Intel is planning to introduce all three at the same time, but the company has already confirmed during its Q4 2020 earnings call that mobile and desktop Alder Lake series will be qualified for production in the second half of 2021.
| Intel 11th Gen and 12th Gen Architectures | |||||
|---|---|---|---|---|---|
| Tiger Lake | Tiger Lake-H | Alder Lake-P | Alder Lake-M | Alder Lake-S | |
| Core Configuration | up to 4 cores | up to 8 cores | up to 6 big + 8 small | up to 2 big + 8 small | up to 8 big + 8 small |
| GPU | Gen12 96EU | Gen12 32EU | Gen12 96EU | Gen12 96EU | Gen12 32EU |
| CPU PCIe | 2x PCIe 4.0 x4 | 1x PCIe 4.0 x16 1x PCIe 4.0 x 4 | 1x PCIe 5.0 x8 2x PCIe 4.0 x4 | PCIe 5.0 x8 or PCIe 4.0 x4 | 2x PCIe 5.0 x8 2x PCIe 4.0 x4 |
| PCH | TGP_LP | TGP_H | ADP_P | ADP_M | ADP_S |
| PCH PCIe Ports | 16 | TBC | 12 | 10 | 28 |
Intel Next-Gen Architectures via Coelacanth Dream
Source: Coelacanth Dream, SiSoftware
