GDDR7 memory up to 36 Gbps per pin
Early adopters can now start testing their next-gen GDDR7 products.
Cadence is ready to ship the first Verification Solutions for GDDR7 technology to companies interested in providing their customers with the most cutting-edge solutions. The announcement of the first VIP (Verification IP) solution from Cadence appears even before JEDEC (Joint Electron Device Engineering Council) has formalized the final specs for this new memory standard.
The GDDR memory is designed for graphics and video processing solutions and has seen many iterations over the last few years. The most recent update being GDDR6 which is now used by AMD Radeon RX 6000 and 7000 GPUs. Meanwhile, NVIDIA and Micron have developed their own standard called GDDR6X, which is the backbone of all high-end RTX 30 and 40 graphics cards.
Cadence has now confirmed that GDDR7 is to use PAM3 signaling, instead of NRZ (non-return to zero/PAM2) used by GDDR6 or PAM4 used by GDDR6X technology. The company claims that PAM3 should have better SNR (signal-to-noise ratio) than PAM4.
According to Anandtech, this means that the GDDR7 modules will offer up to 36 Gbps per pin, significantly improving the speed over the existing standard. Of course, such speeds should not be expected from first-gen GPUs utilizing this technology, but it gives an idea of how far this technology can go.
New Features Added in GDDR7
DRAM uses a single WCK clock for command-address and data latching, while it generates an internal divide-by-4 clock named CK4 that is used as a reference for latencies.
Read clock in GDDR7 can be configured in four different modes from the mode register:
- Always running: As the name suggests, it is always running and stops during sleep modes
- Disable: It stops running when configured in this mode
- Start with RCK Start command: Read clock can be started by issuing the RCK Start command before reading out data. It can be stopped using the RCK STOP command. Host can start/stop as per requirement
- Start with Read: Read clock automatically starts running when DRAM receives any command which involves reading data out. Also, here, it can be stopped using the RCK STOP command
With the help of the last two modes, power usage can be optimized by enabling RCK only during the periods when it is needed.
In GDDR6, only one command can be issued at a time. GDDR7 commands are encoded in such a way that row and column commands use different bits of the CA bus. Hence, two independent commands can be issued in parallel. For example, Bank X can be refreshed by issuing a Refresh per bank command on CA[2:0], while Bank Y can be read by issuing a read command on CA[4:3] at the same time.
GDDR7 uses PAM encoding in high-speed operation for data, CRC, ERR feedback, and the read clock. In PAM3 mode, 256 bits of data are encoded and transferred over 8 WCK clock cycles. It significantly improves the data rate compared to NRZ while having better SNR and eye margins compared to PAM4.
The first GDDR7-based graphics cards should not be expected this year. However, the 2-year cadence for consumer graphics architectures may suggest that such solutions could appear by 2024.