AMD Zen4 cores get 1MB of L2 cache
AMD’s next-gen data center processors have a doubled size of L2 cache.
A fresh leak from Geekbench shows that an unreleased AMD processor with an OPN core of 100-000000479-13 has recently been tested on a validation board called “Quartz”. This OPN code is associated with the AMD EPYC Genoa series, an engineering sample based on A0 silicon to be more specific.
It is a 32-core and 64-thread CPU with a base clock of 1.2 GHz. Given the early state of this sample, this clock will undoubted be higher on a production unit.
The Genoa EPYC CPU has 1 MB of L2 cache. This is twice as much as Naples, Rome or Milan. The L3 cache has not changed since Milan and is kept at 32 MB per chiplet (this sample has CCX, each with 8 cores). However, because Genoa will be offered up to 96 cores, the maximum size of L3 cache will still be higher than its predecessors (with an exception to Milan-X with 3D V-Cache).
This particular sample has been confirmed to be part of Zen4 Genoa series by ExecutableFix in January this year. According to the leaker, there is also a 96-core sample being tested, however we have thus far not seen it on Geekbench.
Other A0 ES' are a 96-core ES2 (OPN 100-000000475-16) and a 32-core ES2 (OPN 100-000000479-10)
— ExecutableFix (@ExecuFix) January 10, 2022
AMD EPYC 7004 Genoa series will officially feature up to 96 cores made in 5 nm process technology. It will be AMD’s first server platform to support DDR5 memory technology as well as PCIe Gen5 interface. According to AMD, it is now on track to launch in 2022. It is currently sampling to customers.
|RUMORED AMD EPYC Processor Series Specifications|
|VideoCardz||7001 “Naples”||7002 “Rome”||7003 “Milan”|
7003 “Milan-X” (*)
|7004 “Genoa”||7004 “Bergamo”||7005 “Turin”|
|Architecture||14nm Zen||7nm Zen2||7nm Zen3||5nm Zen4||5nm Zen4c||Zen5|
|Socket||SP3 (LGA4094)||SP3 (LGA4094)||SP3 (LGA4094)||SP5 (LGA-6096)||SP5 (LGA-6096)||SP5 (LGA-6096)|
8xCCD + 1xI/0
8xCCD + 1xI/O
12xCCD + 1xI/O
12xCCD + 1xI/O
|L2 Cache Per Core||0.5 MB||0.5 MB||0.5 MB||1 MB||TBC||TBC|
|L3 Cache Per CCX||8 MB||8 MB||32 MB / 96 MB (*)||32 MB||TBC||TBC|