AMD Zen4 EPYC “Genoa” features 1MB of L2 cache per core

Published: 28th Mar 2022, 08:21 GMT   Comments

AMD Zen4 cores get 1MB of L2 cache

AMD’s next-gen data center processors have a doubled size of L2 cache. 

A fresh leak from Geekbench shows that an unreleased AMD processor with an OPN core of 100-000000479-13 has recently been tested on a validation board called “Quartz”. This OPN code is associated with the AMD EPYC Genoa series, an engineering sample based on A0 silicon to be more specific.

It is a 32-core and 64-thread CPU with a base clock of 1.2 GHz. Given the early state of this sample, this clock will undoubted be higher on a production unit.

AMD EPYC Genoa Zen4 32-core Engineering Sample, Source: Geekbench

The Genoa EPYC CPU has 1 MB of L2 cache. This is twice as much as Naples, Rome or Milan. The L3 cache has not changed since Milan and is kept at 32 MB per chiplet (this sample has CCX, each with 8 cores). However, because Genoa will be offered up to 96 cores, the maximum size of L3 cache will still be higher than its predecessors (with an exception to Milan-X with 3D V-Cache).

This particular sample has been confirmed to be part of Zen4 Genoa series by ExecutableFix in January this year. According to the leaker, there is also a 96-core sample being tested, however we have thus far not seen it on Geekbench.

AMD EPYC 7004 Genoa series will officially feature up to 96 cores made in 5 nm process technology. It will be AMD’s first server platform to support DDR5 memory technology as well as PCIe Gen5 interface. According to AMD, it is now on track to launch in 2022. It is currently sampling to customers.

AMD 16-core EPYC Genoa processor, Source: VideoCardz

RUMORED AMD EPYC Processor Series Specifications
VideoCardz7001 “Naples”7002 “Rome”7003 “Milan”
7003 “Milan-X” (*)
7004 “Genoa”7004 “Bergamo”7005 “Turin”
Launch201720192021202220222023/2024
Architecture14nm Zen7nm Zen27nm Zen35nm Zen45nm Zen4cZen5
SocketSP3 (LGA4094)SP3 (LGA4094)SP3 (LGA4094)SP5 (LGA-6096)SP5 (LGA-6096)SP5 (LGA-6096)
Modules/Chiplets
 
4xCCD
 
8xCCD + 1xI/0
 
8xCCD + 1xI/O
 
12xCCD + 1xI/O
 
12xCCD + 1xI/O
TBC
Max Cores
 
32C/64T
 
64C/128T
 
64C/128T
 
96C/192T
 
128C/256T
 
256C/512T
Max Clock
 
3.8 GHz
 
3.9 GHz
 
4.1 GHz
TBCTBCTBC
L2 Cache Per Core0.5 MB0.5 MB0.5 MB1 MBTBCTBC
L3 Cache Per CCX8 MB8 MB32 MB / 96 MB (*)32 MBTBCTBC
Memory Channels
 
8-channel
 
8-channel
 
8-channel
 
12-channel
 
12-channel
 
12-channel
Memory Support
 
DDR4-2666
 
DDR4-3200
 
DDR4-3200
 
DDR5-5200
 
DDR5-5200
 
DDR5-6000
PCIe Lanes
 
128x Gen3
 
128x Gen4
 
128x Gen4
 
128x Gen5
TBCTBC
Max cTDP
 
200W
 
280W
 
280W
 
400W
TBC
 
600W

Source: Geekbench via ComputerBase




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