AMD SP5 – a big socket for big CPUs
As we await the formal launch of EPYC Genoa CPUs later this year, the first pictures of the validation boards emerge.
The whole SP5 socket is 7.5 cm high and 7.2 cm wide socket for next-gen Zen4 data-center processors. The EPYC 7004 series codenamed “Genoa” are to feature up to 96 cores, and “Bergamo” with Zen4c cores should offer up to 128 cores. Both series are to be supported by the same SP5 socket.
First photos of the next-gen EPYC motherboard have been posted over at ServeTheHome forums. The design of the socket matches the diagrams that were leaked through last year’s Gigabyte hack. Furthermore, we can see 12-channel DDR5 memory, which is a new feature of the Zen4 EPYC series. PCB diagrams show that each of the four segments of the SP5 socket is connected to one of the subchannels of each of the 12 DIMMs.
The previously leaked diagrams show a sophisticated latching and retention mechanism for the large SP5 processors. At this moment, it is unclear if we are ever to see a SP5 socket for AMD’s HEDT Threadripper series.
The Genoa processors are to feature up o 96 cores and 192 threads. They are based on TSMC N5 process technology and feature Zen4 microarchitecture. AMD has not yet confirmed whether they are planning EPYC 7004 series with 3D V-Cache, just like Milan-X series released last year.
According to AMD, Genoa is currently shipping to first customers and on track to launch by the end of 2022. The Genoa and Bergamo series are to be the first to utilize the SP5 socket, with rumored “Turin” series expected next year at soonest.
|RUMORED AMD EPYC Processor Series Specifications|
|VideoCardz||7001 “Naples”||7002 “Rome”||7003 “Milan”|
7003 “Milan-X” (*)
|7004 “Genoa”||7004 “Bergamo”||7005 “Turin”|
|Architecture||14nm Zen||7nm Zen2||7nm Zen3||5nm Zen4||5nm Zen4c||Zen5|
|Socket||SP3 (LGA4094)||SP3 (LGA4094)||SP3 (LGA4094)||SP5 (LGA-6096)||SP5 (LGA-6096)||SP5 (LGA-6096)|
8xCCD + 1xI/0
8xCCD + 1xI/O
12xCCD + 1xI/O
12xCCD + 1xI/O
|L2 Cache Per Core||0.5 MB||0.5 MB||0.5 MB||1 MB||TBC||TBC|
|L3 Cache Per CCX||8 MB||8 MB||32 MB / 96 MB (*)||32 MB||TBC||TBC|