AMD Sienna Cichlid (Navi21, Big Navi) GPU memory rumors: HBM vs GDDR6

Published: 27th Jul 2020, 13:16 GMT   Comments

Please note that this post is tagged as a rumor.

There is conflicting information on next-generation Navi flagship GPU. 

Rumor 1: Sienna Cichild features HBM memory?

The AMD Sienna Cichlid could allegedly feature a memory bus width up to 2048-bit, indicating a possible use of HBM memory.

AMD Sienna Cichlid is also known as Big Navi or Navi 21. This GPU is expected to be the flagship processor for the upcoming Radeon RX 6900 series based on RDNA2 architecture. Sienna Cichlid first appeared almost two months ago under the same GFX1030 ID as Navi 21.

The new data is not a confirmation, however, it does point towards a possibility that one of the variants of Sienna Cichlid features a memory bus up to 2048-bit: 2 x 8 x 128 = 2048. We do not know if this variant it the same as gaming Radeon RX Navi 21.

A 2048-bit memory bus would indicate that the GPU features two HBM stacks (each requiring 1024-bit bus). This opens a possibility for a 2×8 GB or 2×16 GB (Samsung Flashbolt HBM2e) stack configuration.

AMD Radeon RX 6900 series was expected to feature GDDR6 memory, leaving high-bandwidth memory exclusively for computer-oriented Arcturus GPU. Thus, the news is rather surprising and should still be taken with a grain of salt.

/* HBM Memory Channel Width */
#define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH 128
/* number of umc channel instance with memory map register access */
#define UMC_V8_7_CHANNEL_INSTANCE_NUM 2
/* number of umc instance with memory map register access */
#define UMC_V8_7_UMC_INSTANCE_NUM 8
/* total channel instances in one umc block */
#define UMC_V8_7_TOTAL_CHANNEL_NUM (UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM)
/* UMC regiser per channel offset */
#define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA 0x400

Sienna Cichlid static values for Unified Memory Controller, Source: Freedesktop

static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
{switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID:
adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
adev->umc.funcs = &umc_v8_7_funcs;
break;
default:
break;}}

Sienna Cichlid Graphics Memory Controller Function, Source: Freedesktop

Arcturus

In the case of Arcturus, the GPU for the upcoming Radeon Instinct MI100, the data points towards 4096-bit wide bus: 4 x 8 x 128 = 4096. This would indicate four stacks of HBM memory (and capacities up to 64GB).

/* HBM Memory Channel Width */
#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128
/* number of umc channel instance with memory map register access */
#define UMC_V6_1_CHANNEL_INSTANCE_NUM 4
/* number of umc instance with memory map register access */
#define UMC_V6_1_UMC_INSTANCE_NUM 8
/* total channel instances in one umc block */
#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
/* UMC regiser per channel offset */
#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20 0x800
#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT 0x400

Source: Freedesktop via DisEnchantment (Anandtech Forums)

Rumor 2: Next-Gen Navi features 16GB GDDR6 memory

Somewhat different information has been shared by Wjm47196 on Chiphell forums few days ago. The user is known for various leaks in the past, but it is worth noting that not all of them have turned out to be true. The leaker has said that most rumors that we have been hearing in the past few weeks on Big Navi are not to be taken seriously, simply because AMD has not yet sent finished proofing the PCB for the card. This implies that no one can confirm the final specifications yet, not to mention GPU configuration or performance figures.

The user did however reveal that his sources are confident that the card features 16 GB memory. He later added that it should be 512-bit GDDR6 memory, which does not correlate with the first rumor. This would suggest that the card has GDDR6 memory instead (and honestly as everyone expected).

That said, it is currently not possible to confirm any Big Navi specifications. Even the memory technology, which seemed to be rather locked to GDDR6 is now uncertain.

wjm47196 comments on next-generation Radeon graphics card

AMD Radeon Flagship Models By Generation
VideoCardzR9 290XR9 390XR9 FURY XRX VEGA 64Radeon VIIRumored Big Navi Flagship
GPUHawaii XTGrenada XTFiji XTVega 10 XTVega 20Navi 21
Architecture28nm GCN 2.028nm GCN 2.028nm GCN 3.014nm GCN 5.07nm GCN 5.07nm RDNA 2X
Cores
 
2816
 
2816
 
4096
 
4096
 
3840
TBC
Boost Clock
 
1000 MHz
 
1050 MHz
 
1050 MHz
 
1546 MHz
 
1750 MHz
TBC
FP32 Perf.
 
5.6 TF
 
5.9 TF
 
8.6 TF
 
12.7 TF
 
13.4 TF
TBC
Memory
 
4GB GDDR5
 
8GB GDDR5
 
4GB HBM
 
8GB HBM2
 
16GB HBM2
 
16GB
Memory Bus
 
512-bit
 
512-bit
 
4096-bit
 
2096-bit
 
4096-bit
TBC
Bandwidth
 
320 GB/s
 
384 GB/s
 
512 GB/s
 
483 GB/s
 
1024 GB/s
TBC
TBP
 
300W
 
275W
 
275W
 
295W
 
295W
TBC
MSRP
 
549 USD
 
429 USD
 
649 USD
 
599 USD
 
699 USD
TBC

Source: Chiphell via 3DCenter




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