AMD Infinity Links between Navi 31 MCDs and GCDs have 10x bandwidth density than EPYC and Ryzen chiplets
Some further details on AMD RDNA3 architecture have been posted by Japanese website ASCII. Some slides were not seen before, which is probably why the article has already been taken down.
The new slides detail AMD chiplet technology featured in RDNA3 architecture. They explain the decision behind moving the Infinity Cache outside the GPU die. We also learn that the Infinity Links, the interconnect technology between the memory and GPU is operating at 9.2 Gbps. This is 10 times higher bandwidth density compared to Ryzen and EPYC IFOP (Infinity Fabric On-Package) approach. AMD further claims that the peak bandwidth between MCDs and GCDs is at 5.3 TB/s.
This approach means higher memory latency, but AMD has been working hard to actually lower it compared to Navi 21 on-die cache design. The RDNA3 architecture eliminates higher latency by introducing higher clock rates, by 43% base Infinity Fabric clock and 18% graphics game clock.
Another slide confirms that RDNA3 is designed for ‘significantly increased frequencies’. This refers to 30% higher Static Timing Analysis compared to RDNA2, but the actual clocks rates have only increased by 10%:
- RDNA 2(Radeon RX 6950 XT) : Game 2.1GHz/Boost 2.3GHz
- RDNA 3(Radeon RX 7900 XTX): Game 2.3GHz/Boost 2.5GHz
The slides shared by ASCII are part of a larger RDNA3 architecture presentation. It is very likely that more slides will be shared by other media soon. However, it is not until next month (December 13th) until we hear the full details on Radeon RX 7900 series. This is the launch date of new Radeon cards.
Source: ASCII (cache)