AMD continues its journey departing from the monolithic designs.
AMD patents GPU chiplets
A new patent submitted to the US Patent Office on December 31 describing the AMD approach to potential GPU chiplet design. The manufacturer has outlined the problematic structure of such a design and explained how it would be possible to avoid them in the future.
According to AMD, the GPU designs have been kept in a monolithic state due to various problems with implementation. GPU programming model is inefficient to work with multiple GPUs (that also describes Crossfire configurations), as it is hard to distribute parallelism across multiple active dies in the system. It is also complex and expensive design-wise to synchronize memory content across multiple GPU chipsets, AMD describes.
AMD thinks that it would be possible to avoid such problems by implementing ‘high bandwidth passive crosslinks. According to AMD, the first GPU chipset would be direct ‘communicably coupled’ to the CPU, while each of the GPU chiplets in the array would be coupled to the first GPU via a passive crosslink. In this sense, AMD considered passive crosslink as communication wires between chiplets that are placed on a single interposer. (in multiple layers if needed). Such GPU group would work as a System on a Chip, which is divided into different functional chips.
In conventional GPU designs, each of the GPU features its own last-level cache (LLC), but in order to avoid problematic synchronization, AMD thinks that each of the GPU chiplets should feature its own LLC, but in a way that each of those caches is ‘communicably coupled’ to physical resources so that the cache remains ‘unified and remains coherent across all GPU chiplets’.
AMD has not publically confirmed it is working on a GPU chiplet design. However, there have been rumors that RDNA3+ designs could be based on chiplets. AMD has a lot of experience with multi-chip designs, especially from its Ryzen series and various APUs, including current-gen gaming consoles.
Both competitors, NVIDIA and Intel are also expected to follow this route, which will allow them to produce GPU chips at higher yields. Intel has already confirmed its tile-designed Xe-HP graphics cards, which are expected to make a debut later this year. Meanwhile, NVIDIA is rumored to introduce its first MCM (multi-chip-module design) with the Hopper architecture.
FIG. 1 is a block diagram illustrating a processing system employing high bandwidth passive crosslinks for coupling GPU chiplets in accordance with some embodiments.
FIG. 2 is a block diagram illustrating a sectional view of GPU chiplets and passive crosslinks in accordance with some embodiments.
FIG. 3 is a block diagram illustrating a cache hierarchy of GPU chiplets coupled by a passive crosslink in accordance with some embodiments.
FIG. 4 is a block diagram illustrating a floor plan view of a GPU chiplet in accordance with some embodiments.
FIG. 5 is a block diagram illustrating a processing system utilizing a four-chiplet configuration in accordance with some embodiments.
FIG. 6 is a flow diagram illustrating a method of performing inter-chiplet communications in accordance with some embodiments.