AMD “big.LITTLE” aka heterogeneous computing in Ryzen 8000 series
The next decade will no longer be dictated by the number of cores, but rather the processor’s fabrication node, packaging method, and power effciency. A big role will also be played by heterogeneous architectures.
Later this year Intel will launch its 12th Gen Core Alder Lake processors for desktop and mobile systems. This is not the first architecture to implement Intel’s Hybrid Technology (the first was Lakefield). This is a marketing term for high-efficiency (small) and high-performance (big) core implementation. Most tech users should be more familiar with the term big.LITTLE, which is actually an old name for ARM’s heterogeneous computing architecture, now replaced by DynamIQ.
While heterogeneous CPUs have been used in mobile devices for years, this technology isn’t exactly a domain of modern desktop PCs, where power efficiency is not exactly the biggest concern. The next-generation Windows operating system is rumored to feature a new task scheduling method for such heterogeneous computing, which might just align with Intel’s Alder Lake launch.
While AMD has not really confirmed it is working on such processor design, the leaks have brought us a new codename ‘Strix Point‘, which is associated with Zen5 based APU, supposedly also featuring smaller cores known as Zen4D. The latter is a codename of the smaller core.
Just two days ago, an AMD patent application on ‘task transition between heterogeneous processors’ has been published. This patent was originally filed in December 2019, which suggests AMD has clearly been working on this technology for a long time. The application covers the most important engineering problem of heterogeneous computing, which is how to schedule or transition tasks between different types of cores.
In short, AMD describes that the CPU will relocate tasks between the cores based on one or multiple metrics. These include execution time of the task, a requirement of using memory at maximal performance state, direct access to memory, or a metric of average idle state threshold. If any of such (and others listed in the patent) metrics meet the criteria, the task is then relocated from the first processor core to the second core. Clearly, this is not a very detailed description, but it should provide a brief idea of what is being discussed in the patent, which has not yet been approved.
At this moment, it is believed that Ryzen 8000 series “Strix Point” will be AMD’s first to implement heterogeneous architecture with 3nm Zen5 cores combined with Zen4D on a single package. A desktop variant codenamed “Granite Ridge” is not currently rumored to feature big/small core architecture. It is worth noting that by the time AMD’s heterogeneous CPUs/APUs are available, Intel will already have its Alder Lake architecture on the market. In fact, it is possible that AMD’s first hybrid CPUs will have to compete with Alder Lake’s successor, codenamed Raptor Lake.
|RUMORED AMD Zen Roadmap|