Active Bridge Chiplet with Integrated (Infinity?) Cache
AMD’s latest patent reveals plans for next-gen GPU chiplets.
A patent that published on April 1st (it’s not a joke) reveals what AMD is planning to do with next-generation chiplet designs. In the patent, AMD explains the purpose of its inter-chiplet bridge which would feature an integrated cache. An active bridge idea is a major upgrade over the last patent which features a passive bridge between the chiplets.
The active bridge chiplet would serve as a high-bandwidth die-to-die interconnect between GPU chiplet dies. AMD also explains that it would operate as a memory crossbar with a shared, unified last-level cache (LLC). This would provide inter-chiplet communication and route cross chiplet synchronization signals. The LLC in this case means L3 cache, which in current RDNA2 architecture is called Infinity Cache.
AMD explains that any inter-chiplet communication would be routed through the active bridge chiplet, which would be required to access memory channels on individual GPU chiplets. Furthermore, instead of relying on individual chiplet caches, the whole active bridge cache would act similarly to a monolithic GPU cache – the memory would be addressable as a single registry, which would ensure that from software developers’ perspective no chiplet-specific considerations are required.
The last patent from January and the new patent from April confirm that AMD is devoted to bringing GPU chiplet designs to the market. At this point in time, it is unclear if patents refer to computing architectures such as CDNA, or gaming-oriented RDNA architecture.
Adopting chiplet designs in a traditional graphics rendering pipeline is a complex task that has not been achieved yet. This isn’t a problem for CPU chiplet designs or even GPU chiplets for GPGPUs such as Instinct MI200, Intel Xe-HP(C), or even NVIDIA GH100 (Hopper), all expected to be the industry’s first GPU chiplet architectures. The Active Bridge Chiplet patent that AMD had submitted might refer to their successors.
Source: Free Patents Online