AMD latest GPU chiplet patent reveals plans for active bridge chiplet with integrated cache

Published: 5th Apr 2021, 08:04 GMT   Comments

Active Bridge Chiplet with Integrated (Infinity?) Cache

AMD’s latest patent reveals plans for next-gen GPU chiplets.

Block diagram illustrating a processing system employing active bridge chiplets for coupling GPU chiplets, Source: AMD

A patent that published on April 1st (it’s not a joke) reveals what AMD is planning to do with next-generation chiplet designs. In the patent, AMD explains the purpose of its inter-chiplet bridge which would feature an integrated cache. An active bridge idea is a major upgrade over the last patent which features a passive bridge between the chiplets.

The active bridge chiplet would serve as a high-bandwidth die-to-die interconnect between GPU chiplet dies. AMD also explains that it would operate as a memory crossbar with a shared, unified last-level cache (LLC). This would provide inter-chiplet communication and route cross chiplet synchronization signals. The LLC in this case means L3 cache, which in current RDNA2 architecture is called Infinity Cache.

AMD explains that any inter-chiplet communication would be routed through the active bridge chiplet, which would be required to access memory channels on individual GPU chiplets. Furthermore, instead of relying on individual chiplet caches, the whole active bridge cache would act similarly to a monolithic GPU cache – the memory would be addressable as a single registry, which would ensure that from software developers’ perspective no chiplet-specific considerations are required.

The last patent from January and the new patent from April confirm that AMD is devoted to bringing GPU chiplet designs to the market. At this point in time, it is unclear if patents refer to computing architectures such as CDNA, or gaming-oriented RDNA architecture.

Adopting chiplet designs in a traditional graphics rendering pipeline is a complex task that has not been achieved yet. This isn’t a problem for CPU chiplet designs or even GPU chiplets for GPGPUs such as Instinct MI200, Intel Xe-HP(C), or even NVIDIA GH100 (Hopper), all expected to be the industry’s first GPU chiplet architectures. The Active Bridge Chiplet patent that AMD had submitted might refer to their successors.

Block diagram illustrating a cache hierarchy of GPU chiplets coupled by an active bridge chiplet, Source: AMD

Block diagram illustrating a sectional view of GPU chiplets and active bridge chiplets, Source: AMD

Block diagram illustrating a processing system utilizing a three-chiplet configuration, Source: AMD

Flow diagram illustrating a method of performing inter-chiplet communications, Source: AMD

Source: Free Patents Online

Comment Policy
  • Comments must be written in English.
  • Comments deemed to be spam or solely promotional in nature will be deleted. Including a link to relevant content is permitted, but comments should be relevant to the post topic.
  • Comments containing language or concepts that could be deemed offensive will be deleted. Note this may include abusive, threatening, pornographic, offensive, misleading or libelous language.
  • A failure to comply with these rules will result in a warning and, in extreme cases, a ban.
  • Please note that comments that attack or harass an individual directly will be deleted and such comments will result in a ban.
  • VideoCardz Moderating Team reserves the right to edit or delete any comments submitted to the site without notice.
  • If you would like to appeal for a comment section ban to be removed, please use this page.
  • If you have any questions about the commenting policy, please let us know through the Contact Page.
Hide Comment Policy