AMD EPYC with Zen6 architecture is allegedly codenamed “Venice”

Published: 29th Apr 2022, 21:47 GMT   Comments

Please note that this post is tagged as a rumor.

AMD EPYC “Venice” Zen6 rumors

Some very early rumors on AMD’s first Zen6 designed have emerged.

Tom from Moore’s Law is Dead shared some initial information that he has on the future EPYC implementation of Zen6 architecture. One should note that it is unclear if AMD is even going to keep using Zen naming for its future architecture, but the leaker claims that this information was double-checked and should remain valid for now. This of course does not rule out the possibility of AMD changing their roadmaps in the future.

AMD has only just released its 3rd Gen EPYC update with 3D V-Cache, whereas the EPYC series featuring Zen6 architecture supposedly codenamed “Venice” would arrive 3 generations later. Therefore, it is safe to assume that Venice is a 2024 product at best.

According to the video, EPYC Venice would feature completely redesigned L2/L3 caches and would heavily depend on HBM implementations. At that stage, AMD will probably make use of 3D die stacking technology, so we might be seeing some interesting combinations of large L3 caches and HBM memory working alongside each other.

In terms of specs, not much is known, therefore Zen6 might be using a newer socket and support even faster DDR5 memory variants than Turin. What is clear is that the EPYC 7006 series should feature more than 200 cores, which was already rumored for Zen5 based EPYC.

RUMORED AMD EPYC Processor Series Specifications
VideoCardz7003 “Milan”
7003 “Milan-X” (*)
7004 “Genoa”7004 “Bergamo”7005 “Turin”7006 “Venice”
Launch2021202220222023/20242024/2025
Architecture7nm Zen35nm Zen45nm Zen4cZen5Zen6
SocketSP3 (LGA4094)SP5 (LGA-6096)SP5 (LGA-6096)SP5 (LGA-6096)TBC
Modules/Chiplets8xCCD + 1xIOD12xCCD + 1xIOD12xCCD + 1xIODTBCTBC
Max Cores
 
64C/128T
 
96C/192T
 
128C/256T
 
256C/512T
 
256C+/512T
Max Clock
 
4.1 GHz
TBCTBCTBCTBC
L2 Cache Per Core0.5 MB1 MBTBCTBCTBC
L3 Cache Per CCX32 MB / 96 MB (*)32 MBTBCTBCTBC
Memory Channels
 
8-channel
 
12-channel
 
12-channel
 
12-channel
TBC
Memory Support
 
DDR4-3200
 
DDR5-5200
 
DDR5-5200
 
DDR5-6000
TBC
PCIe Lanes
 
128x Gen4
 
128x Gen5
TBCTBCTBC
Max cTDP
 
280W
 
400W
TBC
 
600W
TBC

Source:

The following video is timestamped
[Moore's Law Is Dead] AMD EPYC Venice ZEN 6 Leak, Lovelace Power Segments, AMD ZEN 4, Intel ARC Launch | April Loose Ends (33,262 views)



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