Please note that this post is tagged as a rumor.
AMD EPYC “Venice” Zen6 rumors
Some very early rumors on AMD’s first Zen6 designed have emerged.
Tom from Moore’s Law is Dead shared some initial information that he has on the future EPYC implementation of Zen6 architecture. One should note that it is unclear if AMD is even going to keep using Zen naming for its future architecture, but the leaker claims that this information was double-checked and should remain valid for now. This of course does not rule out the possibility of AMD changing their roadmaps in the future.
AMD has only just released its 3rd Gen EPYC update with 3D V-Cache, whereas the EPYC series featuring Zen6 architecture supposedly codenamed “Venice” would arrive 3 generations later. Therefore, it is safe to assume that Venice is a 2024 product at best.
According to the video, EPYC Venice would feature completely redesigned L2/L3 caches and would heavily depend on HBM implementations. At that stage, AMD will probably make use of 3D die stacking technology, so we might be seeing some interesting combinations of large L3 caches and HBM memory working alongside each other.
In terms of specs, not much is known, therefore Zen6 might be using a newer socket and support even faster DDR5 memory variants than Turin. What is clear is that the EPYC 7006 series should feature more than 200 cores, which was already rumored for Zen5 based EPYC.
|RUMORED AMD EPYC Processor Series Specifications|
7003 “Milan-X” (*)
|7004 “Genoa”||7004 “Bergamo”||7005 “Turin”||7006 “Venice”|
|Architecture||7nm Zen3||5nm Zen4||5nm Zen4c||Zen5||Zen6|
|Socket||SP3 (LGA4094)||SP5 (LGA-6096)||SP5 (LGA-6096)||SP5 (LGA-6096)||TBC|
|Modules/Chiplets||8xCCD + 1xIOD||12xCCD + 1xIOD||12xCCD + 1xIOD||TBC||TBC|
|L2 Cache Per Core||0.5 MB||1 MB||TBC||TBC||TBC|
|L3 Cache Per CCX||32 MB / 96 MB (*)||32 MB||TBC||TBC||TBC|