AMD EPYC “Venice” with Zen6 CPU cores reportedly uses new SP7 socket

Published: Sep 9th 2023, 08:42 GMT   Comments

AMD next-gen socket SP7 reportedly launches alongside Venice data-center CPUs

The upcoming AMD EPYC processor codenamed “Venice,” featuring Zen6 CPU cores, is said to be compatible with a new SP7 socket.

In the upcoming months, we can expect to hear more about products such as Intel Xeon Falcon Shore, NVIDIA Blackwell, and AMD EPYC Venice. These codenames represent the potential lineup for the 2025 data-center series, which will encompass a range of combinations involving CPUs, GPUs, and XPUs, depending on how the company chooses to name them.

A recent roadmap shared by YuuKi has revealed AMD’s plans to unveil a fresh series of Instinct MI400 products, comprising C, A, and X variants, in addition to their new EPYC Venice processor series. Interestingly, if this roadmap turns out to be accurate, it suggests that the Venice processor will require a new socket known as SP7.

Data-Center Roadmap for 2025, Source: YuuKi-AnS

Additionally, it appears that this series will support 12-channel and 16-channel DDR5 memory configurations, representing an upgrade from the current series, which supports up to 12 channels. In terms of rumors, there is speculation that the Zen6-based Venice product family might potentially become the first AMD architecture to break the 384-core count on a single package. However, it’s important to note that this rumor has not been officially confirmed as of yet.

The AMD Venice series is expected to follow the EPYC Turin series, which features the Zen5 architecture and is reportedly compatible with the SP5 and SP6 sockets currently utilized by EPYC Genoa and Bergamo, featuring Zen4 CPU cores. Unlike the plans laid out for Zen4 and Zen5, AMD has not yet disclosed specific details about the Zen6 EPYC series, apart from confirming its existence on the leaked roadmap.

The introduction of a new socket implies that the Zen6 architecture will likely be packaged differently, possibly to accommodate more chiplets, which could be a strategic move to address Intel’s increasing CPU sizes in the data-center market. Advanced packaging techniques are expected to play a significant role in future CPU architectures as companies explore stacking compute chiplets on top of each other to enhance performance and efficiency.

AMD EPYC Venice CPUs should not be expected sooner than 2025. The company is yet to launch its EPYC 8004 Siena architecture, focusing on telecommunication systems and servers on the edge. These series are said to utilize smaller SP6 socket with reduced memory support to 8 channels.

AMD EPYC Processor Series
Codename7003 “Milan(-X)”9004 “Genoa(-X)”
8004 “Bergamo” *
8004 “Siena”
9005 “Turin(-X)”
8005 “Turin-Dense” *
9006 “Venice”
SocketSP3 (LGA4094)SP5 (LGA-6096)
SP6 (LGA 4094)
SP5 (LGA-6096)
SP6 (LGA 4094)
Max Cores
Max Mem. Channels
12C DDR5
12C DDR5
16C DDR5

Source: YuuKi_AnS

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