AMD 3D V-Cache for Ryzen CPUs has 9 micro pitch bonds
In Hot Chips 33 presentation AMD outlines the future of 3D stacking technology, also sharing first details on its 3D V-Cache stacking.
AMD presentation showcases existing and future 3D stacking technologies. As the TSV (Through Silicon Via), a vertical inter-wafer or inter-die connection, sees an increase in bonds, the technology will be focusing on more complex 3D stacking designs. At this point in time, stacking allows full die-to-die stacking, allowing DRAM on CPUs or CPUs on CPUs. The technology is progressing towards putting separate modules on themselves, such as cores on cores, only to allow macroblocks to be stacked.
Eventually, the TSV pitch will be so dense that module splitting, folding or even circuit splitting will be possible, which will completely revamp the future of processors as we know them today. AMD listed all existing stacking technologies, including Intel’s Foveros/EMIB techniques, implying that AMD considered using this technology for their processors:
AMD had opted for a micro bump pitch of 9 microns, which is a bit denser than future Intel Foveros Direct technology at 10 microns.
AMD expects its 3D Chiplet technology to offer 3x higher interconnect energy efficiency and 15x higher interconnect density.
The manufacturer had already announced its plans for 3D chipsets based on AMD Zen3 CPU, featuring silicon to silicon TSV. The technology will increase the Level3 cache by 64MB. AMD already demonstrated the potential of its 3D V-Cache technology on AMD Ryzen 9 5900X CPU with 32+64MB L3 cache. Such a configuration increases the framerate by 15%, AMD revealed.
Back at Computex 2021, where the technology was first shown, AMD announced that Ryzen CPUs with 3D V-Cache are to be mass-produced by the end of this year.
Source: Ian Cutress (AnandTech), Andreas Schilling (HardwareLuxx), ComputerBase
