While AMD’s FIJI is currently the only graphics processor available with High-Bandwidth-Memory, more GPUs are expected to compete in this technology in the coming months.
JEDEC is an organization responsible for microelectronics standards. Yesterday JEDEC announced an update to “JESD235 High Bandwidth Memory (HBM) DRAM standard”. It’s basically a cookbook to HBM specifications giving us an insight to what is about to come with HBM2.
According to JEDEC HBM2 will be available in 2, 4 and 8-high stacks. It means that the capacity will vary from 1GB to 8GB per stack. Thus according to those specifications if AMD or NVIDIA decide to use 4 stacks with their future Polaris or Pascal GPUs, we should expect graphics cards with up to 32GB memory capacity. However it is very unlikely we will see gaming cards with such capacities, as 32GB frame buffer should remain exclusive to workstation graphics cards for near future.
The cheapest variant of HBM2 is 1GB per stack in 2-Hi variant, so the lowest capacity per layer is 512 MB (HBM1 has 256MB).
Example of HBM2 configurations
I made this chart to illustrate how many different configurations are possible just by using more stacks or layers with lower capacities. This is just a theory based on specifications, it does not mean such configurations will be offered by companies like SKHynix. It is also very unlikely we will see devices with just one stack, but it was important to include it.
If you see any errors, make sure to leave a comment.
|High-Bandwidth-Memory 2 Standard|
|Variant||Layers / Stacks||Visualization||Capacity (Layer / Stack / Total)||Total Bandwidth|
|2-Hi 512 MB||2 / 1||[||]||512 MB / 1 GB / 1 GB||256 GB/s|
|2-Hi 512 MB||2 / 2||[||] [||]||512 MB / 1 GB / 2 GB||512 GB/s|
|2-Hi 512 MB||2 / 4||[||] [||] [||] [||]||512 MB / 1 GB / 4 GB||1024 GB/s|
|2-Hi 1GB||2 / 1||[||]||1 GB / 2 GB / 2 GB||256 GB/s|
|2-Hi 1 GB||2 / 2||[||] [||]||1 GB / 2 GB / 4 GB||512 GB/s|
|2-Hi 1 GB||2 / 4||[||] [||] [||] [||]||1 GB / 2 GB / 8 GB||1024 GB/s|
|4-Hi 512 MB||4 / 1||[||||]||512 MB / 2 GB / 2 GB||256 GB/s|
|4-Hi 512 MB||4 / 2||[||||] [||||]||512 MB / 2 GB / 4 GB||512 GB/s|
|4-Hi 512 MB||4 / 4||[||||] [||||] [||||] [||||]||512 MB / 2 GB / 8 GB||1024 GB/s|
|4-Hi 1 GB||4 / 1||[||||]||1 GB / 4 GB / 4 GB||256 GB/s|
|4-Hi 1 GB||4 / 2||[||||] [||||]||1 GB / 4 GB / 8 GB||512 GB/s|
|4-Hi 1 GB||4 / 4||[||||] [||||] [||||] [||||]||1 GB / 4 GB / 16 GB||1024 GB/s|
|8-Hi 512 MB||8 / 1||[||||||||]||512 MB / 4 GB / 4 GB||256 GB/s|
|8-Hi 512 MB||8 / 2||[||||||||] [||||||||]||512 MB / 4 GB / 8 GB||512 GB/s|
|8-Hi 512 MB||8 / 4||[||||||||] [||||||||] [||||||||] [||||||||]||512 MB / 4 GB / 16 GB||1024 GB/s|
|8-Hi 1 GB||8 / 1||[||||||||]||1GB / 8 GB / 8 GB||256 GB/s|
|8-Hi 1 GB||8 / 2||[||||||||] [||||||||]||1GB / 8 GB / 16 GB||512 GB/s|
|8-Hi 1 GB||8 / 4||[||||||||] [||||||||] [||||||||] [||||||||]||1GB / 8 GB / 32 GB||1024 GB/s|
HBM1 vs HBM2
|DDR3 vs GDDR5 vs HBM1 vs HBM2|
|Prefetch (per I/O)||8||8||2||2|
(2133 per pin)
(8Gbps per pin)
(1Gbps per pin)
(2Gbps per pin)
|tRC||4x – 5xns||40ns(=1.5V)|
|tCCD||4ns (=4tCK)||2ns (=4tCK)||2ns (=1tCK)||2ns (=1tCK)|
|VPP||Internal VPP||Internal VPP||External VPP||External VPP|
|VDD||1.5V, 1.35V||1.5V, 1.35V||1.2V||1.2V|
|Command Input||Single Command||Single Command||Dual Command||Dual Command|
JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard
JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard. HBM DRAM is used in Graphics, High Performance Computing, Server, Networking and Client applications where peak bandwidth, bandwidth per watt, and capacity per area are valued metrics to a solution’s success in the market. The standard was developed and updated with support from leading GPU and CPU developers to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory. JESD235A is available for free download from the JEDEC website.
JESD235A leverages Wide I/O and TSV technologies to support up to 8 GB per device at speeds up to 256 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard supports 2-high, 4-high and 8-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 8 GB per stack.
Additional improvements in the recent update include a new pseudo channel architecture to improve effective bandwidth, and clarifications and enhancements to the test features. JESD235A also defines a new feature to alert controllers when DRAM temperatures have exceeded a level considered acceptable for reliable operation so that the controller can take appropriate steps to return the system to normal operation.
“GPUs and CPUs continue to drive demand for more memory bandwidth and capacity, amid increasing display resolutions and the growth in computing datasets. HBM provides a compelling solution to reduce the IO power and memory footprint for our most demanding applications,” said Barry Wagner, JEDEC HBM Task Group Chairman.
Source: ComputerBase, TechPowerUP, SKHynix