September 7th, 2011
Learn the secrets of taming the GPU for free
Next Tuesday evening in San Jose, Michael Shebanow will give a talk titled “GPU computing: Taming a 23,000 Thread Beast!” Shebanow is a principal research scientist at NVIDIA and he’s got a lot of processor architectures under his belt—the 32-bit and 64-bit x86, SPARC v9, the Motorola 68,000, and the Motorola 88000—so he’s quite familiar with processor architectures and how to get the most computing bandwidth from them. Now he’s working on GPUs at NVIDIA, developing next-generation graphics and unified GPU programming models.
GPUs started out as auxiliary graphics engines for PC and workstation processors. Then someone realized there was a lot of computing power over there in the graphics subsystem that might be put to other uses. At that point, GPUs started to transform into personal supercomputers. Shebanow’s talk will provide a brief history of this evolution and will then focus on the future challenges that await people who would harness this power beyond today’s game-centric sphere.
This talk is one of a series of free lectures sponsored by the Silicon Valley Chapter of the IEEE Computer Society. It will take place on Tuesday, September 13 in the Cadence Building 10 auditorium at 2655 Seely Ave (entrance is at the intersection of Montague and Trimble. The talk starts at 7. Pizza starts at 6:30. The talk is free but there’s a $2 donation request for the pizza (all you care to eat) and soft drink.
Sign up here.
GPUs have fundamentally changed the playing field of high performance computing. Starting out as devices intended only for the display of 3D images, GPUs are now used as supercomputers – attached processors used to accelerate computationally intensive applications. In this talk, using NVIDA GPUs as a basis, I’ll provide a brief history of the GPU, the evolution of GPUs into computing devices, understanding their performance characteristics, and the challenges that lie attaining high performance from these devices.
Michael Shebanow joined NVIDIA in 2003. While at NVIDIA, he has worked on the Tesla product family (G80, GeForce 68xx series) and was one of the lead architects of the Fermi (GF100) family. Also for Fermi, he managed the shader processor architecture team (covered 5 blocks including the SM & L1). He is currently in the research group investigating next generation graphics and unified programming models for GPUs. Prior to NVIDIA, he has managed the development of a number of processors in multiple architecture families (x86-32, x86-64, SPARC v9, 68k, m88k), and was one of three representatives representing Motorola in the Power PC architecture definition committee. While a graduate student at UC Berkeley, he was one of the original developers of HPS (superscalar, dynamically scheduled processor architectures) (started 1984). Dr. Shebanow holds 25 patents in graphics, processor design, and disk controller areas.
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